1. Field of the Invention
The present invention relates to a layout architecture. More particularly, the present invention relates to a layout architecture having high-performance and high-density design.
2. Description of Related Art
FIG. 1 is a layout architecture of conventional standard cells. The conventional standard cells C1-C4 are arranged between a conductor T1 and a conductor T2, and can function as, for example, an amplifier, an adder, a multiplier, and a phase inverter, respectively. Therefore, the standard cells C1-C4 have different widths W1-W4 depending on the complexity of the functions. In FIG. 1, the width W4 is larger than the width W2, thus the layout area of the standard cell C4 is larger than that of the standard cell C2 when having the same height H1. Therefore, the standard cell C4 is suitable for serving as a layout architecture of a circuit with complicated design or a high drive current, while the standard cell C2 is suitable for serving as a layout architecture of a circuit with simple design or a low drive current.
FIG. 2A is a circuit block diagram of a conventional logic device cell. FIG. 2B is a layout view of the conventional logic device cell in FIG. 2B. First, referring to FIG. 2A, the logic device cell in FIG. 2A comprises a pre-driver 20 and a driver 21 for outputting a logic operation signal. The AND gates G1 and G2 of the pre-driver 20 perform logic operation on an input signal and then outputs it into a NOR gate G3, and the NOR gate G3 performs logic operation on the input signal and then outputs it through a buffer B1 of the driver 21.
In the layout shown in FIG. 2 where the pre-driver 20 in FIG. 2A is working, conductors 201 and 204 have a supply voltage VCC and a ground voltage GND, and are respectively connected to a P-type metal oxide semiconductor (PMOS) region 202 and an NMOS region 203. A rectangle layout is formed between the conductors 201 and 204 to function as the pre-driver 20. The driver 21 comprises a PMOS region 212, an NMOS region 213, and the conductors 201 and 204. The driver 21 is different from the pre-driver 20 in that, since the driver 21 needs a high current, the PMOS region 212 and the NMOS region 213 of the driver 21 need a large layout area. However, under the circumstance that the conductors 201-204 have the same height, the layout width of the driver 21 must be larger than that of the pre-driver 20, thereby causing an excessive width of the whole layout. If the layout area is increased by increasing the height between the conductors 201 and 204, although the layout width of the driver 21 is greatly decreased, the area of other standard cells (such as the pre-driver 20) arranged between the conductors 201 and 204 is increased accordingly. However, since the pre-driver 20 is a low-current structure and needs a small device area, the layout area of the pre-driver 20 is wasted due to the inefficient utilization of area.
FIG. 3 is a view of a layout architecture for a logic cell disclosed in U.S. Pat. No. 6,838,713. Referring to FIG. 3, the conventional technology may solve the problem that the conventional driver 21 needs a large layout width, as shown in FIG. 1. A PMOS region 322 of a driver 32 is arranged beneath a conductor 302. As such, the driver 32 can realize the device layout under the height of conductors 301 and 303, and a pre-driver 31 is arranged between the conductors 301 and 302, and has a low height. Such a design may avoid wasting of the layout area of the pre-driver 31. However, one main disadvantage of such a layout architecture is that the architecture adopts a discrete form for the area of the NMOS regions 312 and 323, instead of the PMOS region 322 which appears in the form of a whole block. Due to such discrete form, some of the circuits cannot be shared and should be designed repeatedly, such that the complexity is increased and some layout area is wasted. Besides, the connecting wire is so long that it is difficult for routing.